Semiconductor device comprising an integrated circuit having a vertical bipolar transistor

ABSTRACT

The invention relates to an integrated circuit having a vertical transistor. According to the invention, a transistor having a current amplification β considerably higher than a conventional transistor is obtained due to the fact that the emitter (5) of the transistor has a thickness and a doping level such that the diffusion length of the minority charge carriers injected vertically into the latter is greater than or equal to the thickness of the emitter (5) and the emitter contact region is so small that during operation the total current of minority charge carriers injected from the base into the emitter region is much smaller than the current density of minority carriers injected from the base into the emitter region under the emitter contact region multiplied by the total surface area of the emitter region.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device comprising anintegrated circuit with a vertical bipolar transistor having a collectorregion and an emitter region of a first conductivity type and anintermediate base region of a second conductivity type opposite to thefirst type, wherein the emitter region has a thickness and doping levelsuch that the diffusion length of the minority charge carriers injectedinto the emitter during operation is larger than or equal to thethickness of the emitter region and wherein the emitter is covered by aninsulating layer which is provided with a contact window through whichan electrical contact is provided on an emitter contact region. Theemitter contact region might for instance be the part of the emitterregion directly adjoining said contact or it can for instance beconstituted by an intermediate contact zone of the same conductivitytype but of a higher dopant concentration than the emitter region.

In order to obtain a maximum amplification, it is considered hithertothat either only the doping profile of the base or only the dopingprofile of the emitter can be influenced while maintaining theelectrical emitter contact zone on the largest possible emitter surface.This permits of optimizing inter alia the value of the currentamplification, which is proportional to the injection efficiency of theemitter-base junction defined by the ratio λ_(O) between the current ofminority charge carriers injected into the base and that injected intothe emitter.

The present invention is based on the recognition that in the case inwhich the thickness and the doping level of the emitter region are suchthat the diffusion length of the minority charge carriers injectedvertically into the emitter is larger than the said thickness, theinjection phenomena would have to be considered in a quite differentmanner.

In French Patent FR-2,592,525, the injection phenomenon concerning thelateral transistors has already been envisaged. The basic idea then wasto minimize the vertical injection into the base of the transistor infavour of the lateral injection while utilizing the fact that thevertical injection into the emitter is considerably smaller under thesurface isolation than under a contact zone. An analysis utilizing asimplified model of the phenomenon then has permitted of determining theoptimum conditions of demensions of the emitter contact surface leadingto an optimum amplification.

On the contrary, for a vertical transistor, a high amplification canonly be obtained by promoting to the highest possible extent thevertical injection into the base, and the preceeding remarks logicallylead to the conventional theory according to which the emitter contactzone must occupy the largest possible emitter surface because theinjection under a (metal) contact zone is much higher than under theisolation.

SUMMARY OF THE INVENTION

The object of the invention i.a. consists in considerably increasing,preferably at least by a factor 10, this injection efficiency solely bythe modification of the geometry of the surface of the emitter.

According to the invention a semiconductor device of the kind describedabove is characterized in that the emitter contact region is so smallthat during operation the total current of minority charge carriersinjected from the base into the emitter region is much smaller than thecurrent density of minority carriers injected from the base into theemitter region under the emitter contact region multiplied by the totalsurface area of the emitter region.

The inventor has been able to ascertain, however, that the mechanism ofthe vertical injection was anything but that which would be expected andthat in the aforementioned case and paradoxically with the same emittersurface a reduction of the surface of the emitter contact zone exerts avery favorable influence on the global injection efficiency of theemitter-base junction and hence on the current amplification of thetransistor.

Particularly the ratio between the area of the emitter surface and thatof the emitter contact region is at least equal to 5 and preferablyequal or larger than 10 for instance between 20 and 300. This results inthat the global injection efficiency of the emitter-base junction ismultiplied by a considerable factor, which may exceed 20. Thus verticaltransistors are obtained whose current amplification is much higher thanin a comparable conventional transistor and even may exceed 1000.

According to a preferred embodiment, the base and/or the collector havean annular highly doped contacting region.

The invention also relates to a method of manufacturing a semiconductordevice comprising a semiconductor device body with an integrated circuithaving a vertical bipolar transistor comprising steps of, forming afirst region of a first conductivity type above a part of a substrate ofa second conductivity type opposite to the first type, the first regionadjoining a major surface of the body, as well as forming a secondregion of the second conductivity type included in the first region,such that the first and second regions are arranged so that they formthe base region and the emitter region respectively of the transistor,whose collector region is constituted by the said part of the substrate,providing an insulating layer on the major surface of said semiconductorbody, forming a contact window in the insulating layer above an emittercontact region and providing an electrical contact, through the contactwindow to the emitter contact region, characterized in that the emitterregion is given a thickness and a doping level such that the diffusionlength of the minority charge carriers vertically injected into thelatter is larger than or equal to the thickness of the said emitterregion, in that the contact window is given lateral dimensionssubstantially equal to the minimum permissible dimension in the method,and in that the distance between the contact window and the edge of theemitter is taken at least over part of the periphery of the said zone tobe at least equal to three times the nominal alignment tolerance of themethod.

BRIEF DESCRIPTION OF THE DRAWING

The invention will be more clearly understood after reading thefollowing description, given by way of non-limitative example, inconjunction with the drawings, in which:

FIGS. 1a and 1b show in plan view and in sectional view XX,respectively, a first embodiment of the invention;

FIGS. 2a and 2b show in plan view and in sectional view, respectively, apreferred embodiment of the invention;

and FIGS. 3 and 4 show the curves representing the value of theamplification β as a function of S_(E) /S_(M) and of the collectorcurrent I_(c), respectively.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

According to FIGS. 1a and 1b, the integrated circuit has a substrate 1of the p-type comprising a part 21 on which a region 2 of the n-type isdeposited by epitaxy, which is surrounded by an isolation island 20 ofSiO₂ (deep oxide). At the center of the region 2, a p-type region 5 isimplanted (thickness of the layer 0.6 μm) (R=500 Ω/) so that a region 3is left between the lower part of the latter and the part 21 of thesubstrate 1. The regions 5, 3 and the part 21 of the substrate 1constitute the emitter, the base and the collector, respectively, of avertical transistor. The remaining part of the region 2 serves as basecontacting region from the upper surface of the region 2, whichconstitutes a part of the major surface of the integrated circuit.

With a view to the said contacting regions, the major surface of theintegrated circuit is coated at least on the upper surface of the region2 (inclusive of the region 5) with an isolating layer 6 (thin oxide)having an emitter contact window 10 and at least one base contact window14. In the base contact windows 14, local n⁺ regions are diffused, whichare intended in known manner to facilitate the contacting.

An emitter metallization surface has at least one region 12 situated inthe window 10 so as to form an electrical emitter contact only in alocal region of the latter. As will be shown hereinafter, thisdisposition is paradoxically favorable for obtaining a high currentamplification μ for the vertical transistor.

At least one base metallization surface has at least one region 16situated in the corresponding window 14 so as to form an electrical basecontact on a substantial part of the surface available. In this case,two surfaces are shown, which are situated on either side of the emitterregion 5.

Let it be assumed that I_(M) is the electron injection current in theemitter 5 under the emitter contact zone 5. Let it be assumed that I_(X)is the injection current of electrons in the emitter 5 under the oxidelayer 6. Let is finally be assumed that I_(C) is the injection currentof holes in the base. The emitter contact zone 12 has a surface S_(M),the oxide layer 6, in its part covering the emitter 5 has a surfaceS_(X) and the emitter 5 has a surface S_(E) =S_(X) +S_(M).

The Applicant has been able to show that in the case in which theemitter 5 has a doping and a thickness such that the diffusion length ofthe minority charge carriers injected into the emitter was greater thanor equal to the thickness of the emitter, the various currents I_(M),I_(X) and I_(C) could all be expressed as a function of the base-emittervoltage V_(BE) of the transistor, independently of any geometricalfactor. It follows that: ##EQU1## J_(M), J_(X) and J_(O) are constantsrepresenting the current densities of injection of electrons under ametallic layer, of electrons under an oxide layer and of holes into thebase, respectively.

This basic property of the vertical injection, permits of obtaining theexpected results.

In fact, the amplification β is then expressed by: ##EQU2## It onlydepends upon the ratio S_(E) /S_(M) and is higher as this ratio ishigher. The variation of the curve of amplification is given in FIG. 3.It increases upto an asymptotic value J_(O) /J_(X). The ratio J_(O)J_(X) represents the injection efficiency λ_(O) according to theconventional junction theory.

By way of example, the following values are given: ##EQU3## with a basehaving a doping of 2.10¹⁶ atoms/cm³ and a depth of 0.8 μm.

a) For S_(E) =2350 μ², S_(M) =16 μm². If it is assumed that S_(E) /S_(M)=146, an amplification β of 1620 is measured (for a calculatedamplification of 1765).

b) for S_(E) /S_(M) or the order of 5 to 7, an amplification β of about150 is measured.

The formula given above neglects the influence of the lateral injectioninto the base, which explains partly the differences between calculatedand measured values, which differences remain within reasonable limits.

FIG. 4 shows the variation of the curve giving the value of theamplification β as a function of the collector current I_(C) at acollector-base voltage zero. The slight decrease of the amplification atlow level is due mainly to the currents I_(X), which could rather berepresented by the following equation: ##EQU4## M_(X) being a constanthaving a value slightly larger than unity.

On the contrary, it is verified by experiments that the current I_(C)accurately follows the relation (3).

The decreases of the amplification at high current is the consequence ofseveral effects occurring successively.

These effects are the influence of the base resistance, the increasinglyhigher level of the injection into the base and the state of saturationattained due to the collector resistance.

FIGS. 2a and 2b show a preferred embodiment of the invention, in whichthe base is provided with an n⁺ base contacting ring 24 extending overthe whole depth of the base and permitting of reducing the baseresistance and with a p⁺ collector contacting ring 30 so as to reducethe collector resistance by establishing the collector contact throughthe major surface of the circuit (metallization 31). The rings 24 and 30are mutually isolated by a ring 20' of deep oxide formed simultaneouslywith the layer 20 of deep oxide.

The embodiments shown relate to the case of isolation by oxide. Itstands to reason that the invention is not limited to this kind ofprocess and that it may also be applied, for example, to the case ofintegrated circuits having a junction isolation. Although the inventionhas been described for the case of transistors of the pnp type, itshould be noted that it may also be applied to the case of transistorsof the npn type.

I claim:
 1. A semiconductor device comprising an integrated circuit witha vertical bipolar transistor having a collector region and an emitterregion of a first conductivity type and an intermediate base region of asecond conductivity type opposite to the first type, wherein the emitterregion has a thickness and doping level such that the diffusion lengthof the minority carriers injected into the emitter during operation isat least equal to the thickness of the emitter region and wherein theemitter is covered by an insulating layer which is provided with acontact window through which an electrical contact is provided on anemitter contact region, characterized in that the ratio between the areaof the emitter region and the area of the emitter contact region is atleast equal to 5, thereby causing, during operation, the total currentof minority carriers injected from the base into the emitter region tobe much smaller than the current density of minority carriers injectedfrom the base into the emitter region under the emitter contact regionmultiplied by the total surface area of the emitter region.
 2. Asemiconductor device comprising an integrated circuit with a verticalbipolar transistor having a collector region and an emitter region of afirst conductivity type and an intermediate base region of a secondconductivity type opposite to the first type, wherein the emitter regionhas a thickness and doping level such that the diffusion length of theminority carriers injected into the emitter during operation is at leastequal to the thickness of the emitter region and wherein the emitter iscovered by an insulating layer which is provided with a contact windowthrough which an electrical contact is provided on an emitter contactregion, characterized in that the ratio between the area of the emitterregion and the area of the emitter contact region is at least equal to10, thereby causing, during operation, the total current of minoritycarriers injected from the base into the emitter region to be muchsmaller than the current density of minority carriers injected from thebase into the emitter region under the emitter contact region multipliedby the total surface area of the emitter region.
 3. A semiconductordevice comprising an integrated circuit with a vertical bipolartransistor having a collector region and an emitter region of a firstconductivity type and an intermediate base region of a secondconductivity type opposite to the first type, wherein the emitter regionhas a thickness and doping level such that the diffusion length of theminority carriers injected into the emitter during operation is at leastequal to the thickness of the emitter region and wherein the emitter iscovered by an insulating layer which is provided with a contact windowthrough which an electrical contact is provided on an emitter contactregion, characterized in that the ratio between the area of the emitterregion and the area of the emitter contact region lies between 20-300,thereby causing, during operation, the total current of minoritycarriers injected from the base into the emitter region to be muchsmaller than the current density of minority carriers injected from thebase into the emitter region under the emitter contact region multipliedby the total surface area of the emitter region.
 4. An integratedcircuit as claimed in one of claims 1, 2, or 3, characterized in thatthe base (3) has a highly doped region (24) of the second conductivitytype extending along its whole periphery.
 5. An integrated circuit asclaimed in any one of claims 1 to 3, characterized in that the collectorregion has a highly doped contacting region (30) of the firstconductivity type.